1. Field of the Invention
The invention relates generally to a method of erasing a flash memory device, and more particularly to, a method of erasing a flash memory device by which a flow of leakage current can be reduce through bit lines.
2. Description of the Prior Art
In general, a flash memory device having an electrical program and erasure function is consisted of a memory cell array and peripheral circuits. The memory cell array is consisted in such a manner that a plurality of memory cells for storing information are connected between word lines and bit lines, for example, in a matrix manner. The peripheral circuits are consisted of a circuit that outputs the information stored at the memory cell to the outside or stores information inputted from the outside at the memory cell.
As mentioned above, the memory cell at which information is stored is consisted of a gate electrode formed on a semiconductor substrate, and a source and a drain both formed in the semiconductor substrate on both sides of the gate electrode. The gate electrode is consisted of a structure in which a tunnel oxide film, a floating gate, a dielectric film and a control gate ate stacked.
Then, the principle of the program operation for storing information at the memory cell and the erasure operation for erasing the stored information will be explained shortly as follows.
First, if a program bias voltage is applied the control gate, the source and the drain in a selected memory cell, respectively, hot carriers generated at the semiconductor substrate are injected into the floating gate through the tunnel oxide film. Thus, as the threshold voltage of the memory cell is increased over a certain level, the memory cell is kept at a program state.
On the other hand, if an erasure bias voltage is applied to the control gate, the source and the drain, respectively, hot carriers injected into the floating gate are discharged to the semiconductor substrate. Thus, as the threshold voltage of the memory cell is reduced below a certain level, the memory cell is kept at an erasure state.
Then, the erasure procedure of the flash memory device driven by this principle will be below explained by reference to FIGS. 1 and 2.
The conventional flash memory device has a chip erasure function. The chip erasure function is one to erase memory cells in a memory cell array consisted of a plurality of sectors, which applies an erasure bias voltage all the memory cells in the first sector selected and then applies an erasure verification bias voltage to the memory cells in the sector to very whether respective memory cells have been erased or not. If all the memory cells in the selected sector is erased by this erasure operation, a recovery verification operation for discriminating over-erased memory cells and a recovery operation for recovering the threshold voltages of the over-erased memory cells to a certain level are sequentially implemented.
At this time, the recovery verification operation is a procedure of checking whether or not any leakage current flows through a drain of the memory cell, that is, bit lines, by applying, for example, 0V, 1V and 0V, to a control gate, a drain and a source in the selected memory cell, respectively. In case of the over-erased memory cell, the leakage current flowed through the bit line is generated. Therefore, the recovery operation must be implemented in order to recover the threshold voltage of the over-erased memory cell. Thus, in the recovery operation, voltages of 0V, 5.5V and 0V are applied to the control gate, the drain and the source in the memory cell, respectively.
However, when the memory cell is erased using the conventional erasure method mentioned above, the leakage currents flowed through the erased memory cells are different depending on the temperature of the device. Particularly, when the leakage current is measured after the erasure operation is implemented at low temperature, the flow of the leakage current is very great.
FIG. 1 is a graph showing a flow of a leakage current through bit lines, measured after erasure operation is implemented at room temperature;
FIG. 2 is a graph showing a flow of a leakage current through bit lines, measured after erasure operation is implemented at high temperature (for example, 90.degree. C.). As can be seen from the graphs, when the leakage current is measured at room temperature after the erasure operation is implemented at room temperature, the greatest leakage current is less than 7 .mu.m. However, when the leakage current is measured at high temperature after the erasure operation is implemented at room temperature, the greatest leakage current is about 14 .mu.m. Thus, it can be seen that the amount of the leakage current measured at high temperature is twice that measured at room temperature. Therefore, the program characteristic of the device is degraded since the leakage current exceeding the program verification current (about 10.about.27 .mu.m depending on the device) is generated.